Conventional high speed serial communication interface drivers typically consume a relatively large amount of power due to the analog biasing requirements (current flows all the time). The relationship between the currents consumed by the driver and the actual signal amplitude generated at the output of the driver can vary widely depending on the driver topology. Examples of conventional serial interface drivers are illustrated in FIGS. 1 and 2.
FIG. 1 illustrates a CML example including resistors R1, R2 and R3, transistors M1 and M2, and output driver 18. The transistors M1 and M2 are controlled by complementary digital inputs INP and INN. The circuit of FIG. 1 effectively has double 50 ohm termination, and the differential pair M1, M2 steers current to the output. Because of current division between the internal (R1 and R2) and external (R3) termination, only one-fourth of the output bias current I0 is used to generate the output voltage Vo. A 10 mA output stage bias current is required to produce a 250 mV output swing. In FIG. 1, the currents I0, I1 and I2 illustrate the operation of the circuit with transistor M2 turned on, transistor M1 turned off and I0=10 mA.
FIG. 2 illustrates a prior art LVDS example including transistors M20-M23, resistors R3 and R4, and output driver 18. The circuit of FIG. 2 provides improved efficiency over the circuit of FIG. 1, because the “switch box” formed by transistors M20-M23 steers current to the output more effectively. Due to the double termination provided by R3 and R4, the effective impedance seen by the output driver 18 is 50 ohms differential. In the circuit of FIG. 2, a 500 mV output swing can be produced from a 10 mA bias current. The currents I0, I1 and I2 illustrate operation of the circuit of FIG. 2 with transistors M23 and M21 turned on, transistors M20 and M22 turned off, and I0=10 mA.
Comparing the power consumption of the prior art serial interface driver circuits of FIGS. 1 and 2, to produce a constant output voltage of 500 mV, and assuming a 2.5 V power supply, the circuit of FIG. 1 will have current and power requirements of 20 mA and 50 mW, and the circuit of FIG. 2 will have current and power requirements of 10 mA and 25 mW.
It is desirable in view of the foregoing to provide for serial communication interface drivers with current and power requirements that improve upon the performance of prior art serial communication interface drivers.